A new chip architecture from IBM can integrate nearly 100 billion transistors on a chip the size of a human fingernail—nearly twice the transistor density of the company’s previous generation of chip technology. The resulting improvement in chip compute performance and energy efficiency comes from what IBM describes as the “world’s first sub-1 nanometer chip technology” for AI data centers.

“It’s not just an incremental step, it’s a meaningful leap forward,” said Jay Gambetta, director of IBM Research and IBM Fellow, in an advance media briefing. He described the new chip technology as pointing to a future where computing becomes significantly more powerful without a corresponding increase in energy consumption.

Unpacking this claim reveals that “world’s first sub-1 nanometer chip technology” is more about achieving performance improvements through advanced architecture rather than actual physical feature sizes below 1 nanometer. IBM’s new ‘nanostack’ architecture effectively delivers the anticipated computing gains of a sub-1 nanometer chip, named the 7 angstrom node for its 0.7-nanometer node.

It’s worth noting that such node numbers no longer correlate with physical dimensions as they did in earlier eras. For decades, the actual physical feature sizes have been different from the node numbering system used to describe chip generations.

This advancement could mean significant improvements for AI data centers and further developments in computing technology, possibly leading to more powerful but less energy-hungry devices in the near future.